This invention relates generally to read only memory circuits, and more particularly, to precharge and output enable methods for reducing power consumption of read only memory circuits.
There is a continuing need for increased memory capacity and reduced power consumption of read only memory (ROM) and other memory storage devices. ROM circuits are included on dedicated ROM integrated circuits and as circuit blocks on other integrated circuits such as ASICs. FIG. 1 shows a timing diagram for a conventional ROM circuit having a clock signal `CLK`, an address signal `Address` and a data signal `Data.` According to standard ROM operation, the ROM circuitry is precharged during each access cycle to assure that a valid data value is read from a ROM cell. Without precharging, the data corresponding to a desired address may be corrupted.
Conventionally, the entire ROM core is precharged during each access cycle. During one phase of the access cycle precharging occurs. During a subsequent phase, data is read. In a typical embodiment the step of precharging includes charging a capacitance on each bit line of the ROM core. Discharging then occurs during a subsequent read phase of the access cycle. Referring to the timing diagram of FIG. 1, a ROM is in a precharge mode when signal nCS is unasserted (e.g., logic 1). During such mode the address decoders and output drivers are disabled, and the signal `precharge` is active (e.g., logic 1). The precharge signal is given a long rise time to charge up the column slowly so that it does not introduce electromagnetic interference in a ROM cell. Signal `rowdecsel` is the enable signal for the row and column decoders and is the logical inverse of signal nCS.
When nCS is asserted (e.g., logic 0), the precharge mode is over and discharging/reading begins. Signal rowdecsel becomes active (e.g., logic 1) to enable row and column decoding. The address bus latches. Soon after signal nCS is asserted, signal nRD also is asserted (e.g., logic 0) to enable the output drivers. Signal `out enable` is the output buffer enable signal and is the logical NOR of signals nCS and nRD. After signal `out enable` becomes active (e.g., logic 0) the data signal becomes valid (e.g., portion 12 of signal Data.
In an exemplary ROM circuit each bit line has a capacitance of approximately 2 picofarads which is precharged and discharged. For a 1024 column design, approximately 2048 pf are charged during each access cycle. Accordingly, considerable power is consumed by large ROMs having many columns. It is desirable to implement more efficient ROM circuits which consume relatively less power without compromising operability or performance.